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P-CHANNEL 55V - 0.016 - 80A TO-220 STripFETTM II POWER MOSFET
TYPE STB80PF55
s s s s
STP80PF55
PRELIMINARY DATA
VDSS 55 V
RDS(on) < 0.018
ID 80 A
TYPICAL RDS(on) = 0.016 EXCEPTIONAL dv/dt CAPABILITY 100% AVALANCHE TESTED APPLICATION ORIENTED CHARACTERIZATION
1 2
3
DESCRIPTION This Power MOSFET is the latest development of STMicroelectronis unique "Single Feature SizeTM" strip-based process. The resulting transistor shows extremely high packing density for low onresistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. APPLICATIONS s MOTOR CONTROL s DC-DC & DC-AC CONVERTERS
TO-220
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol VDS VDGR VGS ID(*) ID IDM(*) Ptot dv/dt (1) EAS (2) Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuos) at TC = 25C Drain Current (continuos) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Peak Diode Recovery voltage slope Single Pulse Avalanche Energy Storage Temperature Max. Operating Junction Temperature Value 55 55 16 80 57 320 300 2 7 1.4 -55 to 175 Unit V V V A A A W W/C V/ns mJ C
(*) Pulse width limited by safe operating area
(*) Current Limited by Package
Note: For the P-CHANNEL MOSFET actual polarity of voltages and current has to be reversed (1) ISD 40A, di/dt 300A/s, VDD V (BR)DSS, Tj T JMAX. (2) Starting T j = 25 oC, ID = 80A, VDD = 40V
February 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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STP80PF55
THERMAL DATA
Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Thermal Resistance Junction-ambient Maximum Lead Temperature For Soldering Purpose Max Max Typ 0.5 62.5 300 C/W C/W C
ELECTRICAL CHARACTERISTICS (Tcase = 25 C unless otherwise specified) OFF
Symbol V(BR)DSS IDSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 A, VGS = 0 VDS = Max Rating VDS = Max Rating TC = 125C VGS = 16 V Min. 55 1 10 100 Typ. Max. Unit V A A nA
IGSS
ON (*)
Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS VGS = 10 V ID = 250 A ID = 40 A Min. 2 Typ. 3 0.016 Max. 4 0.018 Unit V
DYNAMIC
Symbol gfs Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS > ID(on) x RDS(on)max, ID = 40 A VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. 32 5500 1130 600 Max. Unit S pF pF pF
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STP80PF55
ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON
Symbol td(on) tr Qg Qgs Qgd
(*)
Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge
(*)
Test Conditions ID = 40 A VDD = 25 V RG = 4.7 VGS = 10 V (Resistive Load, Figure 3) VDD= 25 V ID = 80 A VGS= 10V
Min.
Typ. 35 190 190 27 65
Max.
Unit ns ns
258
nC nC nC
SWITCHING OFF
Symbol td(off) tf tr(Voff) tf tc
Parameter Turn-off Delay Time Fall Time Off-voltage Rise Time Fall Time Cross-over Time
(*)
Test Conditions ID = 40 A VDD = 25 V RG = 4.7 VGS = 10 V (Resistive Load, Figure 3) ID = 80 A Vclamp = 40 V RG = 4.7 VGS = 10 V (Inductive Load, Figure 5)
Min.
Typ. 165 80 60 40 85
Max.
Unit ns ns ns ns ns
SOURCE DRAIN DIODE
Symbol ISD ISDM (*) VSD (*) trr Qrr IRRM
Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current
Test Conditions
Min.
Typ.
Max. 80 320
Unit A A V ns nC A
ISD = 80 A
VGS = 0 110 495 9
1.3
di/dt = 100A/s ISD = 80 A VDD = 25 V Tj = 150C (see test circuit, Figure 5)
(*) Pulse width [ 300 s, duty cycle 1.5 %. (*) Pulse width limited by TJMAX
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STP80PF55
Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times
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STP80PF55
TO-220 MECHANICAL DATA
DIM. MIN. A C D D1 E F F1 F2 G G1 H2 L2 L4 L5 L6 L7 L9 DIA. 13.0 2.65 15.25 6.2 3.5 3.75 0.49 0.61 1.14 1.14 4.95 2.4 10.0 16.4 14.0 2.95 15.75 6.6 3.93 3.85 0.511 0.104 0.600 0.244 0.137 0.147 4.40 1.23 2.40 1.27 0.70 0.88 1.70 1.70 5.15 2.7 10.40 0.019 0.024 0.044 0.044 0.194 0.094 0.393 0.645 0.551 0.116 0.620 0.260 0.154 0.151 mm TYP. MAX. 4.60 1.32 2.72 MIN. 0.173 0.048 0.094 0.050 0.027 0.034 0.067 0.067 0.203 0.106 0.409 inch TYP. MAX. 0.181 0.051 0.107
A
C
D1
L2
F1
D
G1
E
Dia. L5 L7 L6 L4
P011C
L9
F2
F
G
H2
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STP80PF55
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics (R) 2002 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
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